The present invention relates to an oscillator circuit and a delay circuit, and more particularly to an oscillator circuit which may be integrated in a semiconductor integrated circuit and which is capable of changing oscillation frequency, duty ratio and phase as well as a delay circuit which is capable of changing delay time, rise time and fall time.
In the Japanese laid-open patent publication No. 59-86326, a conventional oscillator circuit is disclosed which is capable of changing oscillation frequency and duty ratio.
FIG. 1 is a circuit diagram illustrative of a conventional oscillator circuit which is capable of changing oscillation frequency and duty ratio. The conventional oscillator circuit has a plurality of invertors INV1, INV2, . . . INV2k+1 (k: natural number) which are connected in series to each other on an odd stage to form a ring oscillator. The conventional oscillator circuit has a plurality of p-channel MOS field effect transistors connected between the invertor and the high voltage line as well as a plurality of n-channel MOS field effect transistors connected between the invertor and the ground line. The conventional oscillator circuit also has a gate voltage control unit 2 which operates to output gate signals to individual p-channel and n-channel MOS field effect transistors.
The invertor INV1 has a power terminal which is connected in series to a p-channel MOS field effect transistor TP1 which is connected to a high voltage line. A drain of the p-channel MOS field effect transistor TP1 is connected to the high voltage line, whilst a source of the p-channel MOS field effect transistor TP1 is connected to the power terminal of the inverter INV1. The invertor INV1 also has a ground terminal which is connected in series to an n-channel MOS field effect transistor TN1 which is connected to a ground line. A drain of the n-channel MOS field effect transistor TN1 is connected to the group terminal of the n-channel MOS field effect transistor TN1, whilst a source of the n-channel MOS field effect transistor TN1 is connected to the ground line. A gate of the p-channel MOS field effect transistor TP1 is connected to the gate voltage control unit 2 for receiving a gate signal GP1. A gate of the n-channel MOS field effect transistor TN1 is also connected to the gate voltage control unit 2 for receiving a gate signal GN1.
Also, the invertor INV2 has a power terminal which is connected in series to a p-channel MOS field effect transistor TP2 which is connected to a high voltage line. A drain of the p-channel MOS field effect transistor TP2 is connected to the high voltage line, whilst a source of the p-channel MOS field effect transistor TP2 is connected to the power terminal of the inverter INV2. The invertor INV2 also has a ground terminal which is connected in series to an n-channel MOS field effect transistor TN2 which is connected to a ground line. A drain of the n-channel MOS field effect transistor TN2 is connected to the ground terminal of the n-channel MOS field effect transistor TN2, whilst a source of the n-channel MSO field effect transistor TN2 is connected to the ground line. A gate of the p-channel MOS field effect transistor TP2 is connected to the gate voltage control unit 2 for receiving a gate signal GP2. A gate of the n-channel MOS field effect transistor TN2 is also connected to the gate voltage control unit 2 for receiving a gate signal GN2.
Also, the invertor INV2K+2 has a power terminal which is connected in series to a p-channel MOS field effect transistor TP2K+2 which is connected to a high voltage line. A drain of the p-channel MOS field effect transistor TP2K+2 is connected to the high voltage line, whilst a source of the p-channel MOS field effect transistor TP2K+2 is connected to the power terminal of the inverter INV2K+2. The invertor INV2K+2 also has a ground terminal which is connected in series to an n-channel MOS field effect transistor TN2K+2 which is connected to a ground line. A drain of the n-channel MOS field effect transistor TN2K+2 is connected to the ground terminal of the n-channel MOS field effect transistor TN2K+2, whilst a source of the n-channel MOS field effect transistor TN2K+2 is connected to the ground line. A gate of the p-channel MOS field effect transistor TP2K+2 is connected to the gate voltage control unit 2 for receiving a gate signal GP2K+2. A gate of the n-channel MOS field effect transistor TN2K+2 is also connected to the gate voltage control unit 2 for receiving a gate signal GN2K+2. The gate signals outputted from the gate voltage control unit 2 are in correspondence to the oscillation frequency and the duty ratio.
Operations of the above circuit will be described as follows. If the p-channel MOS field effect transistor TP1 is operated in a non-saturation region, then an ON-resistance of the p-channel MOS field effect transistor TP1 is given by the following equation. EQU Ron={.beta.(VGS-Vth-VDS/2)}.sup.-1 ( 1)
where .beta. is the capacity coefficient, VGS is the gate source voltage, VDS is the source drain voltage and Vth is the threshold voltage. This means that the ON-resistance Ron is added between the power terminal of the invertor INV1 and the high voltage line. It may equivalently be considered that the current driving ability of the invertor INV1 is controlled by a gate output voltage GP1 from the gate voltage control unit 2. The above descriptions about the ON-resistance of the p-channel MOS field effect transistor TP1 may be applicable to other p-channel and n-channel MOS field effect transistors. The current driving ability of the logic gates on individual stages which forms a ring-oscillator are controllable by the gate voltage outputted from the gate voltage control unit 2 whereby the oscillation frequency and the duty ratio can be changed.
More concretely, in order to rise the oscillation frequency, it is required that the current driving ability of the logic gate on each stage is increased. Therefore, the gate voltage GP1, GP2 . . . GP2k+1 to be applied to the gates of the p-channel MOS field effect transistors are dropped whilst the gate voltage GN1, GN2 . . . GN2k+1 to be applied to the gates of the n-channel MOS field effect transistors are risen.
In order to increase the duty ratio, it is required that the falling speed of the output from the logic gates on the odd stages and the rising speed of the output from the logic gates on the even stages are decreased as well as that the rising speed of the output from the logic gates on the odd stages and the falling speed of the output from the logic gates on the even stages are increased. Therefore, the gate voltages GP1, GN1, GP3, GN3 GP2K+1, and GN2k+1 to be applied to the gates of the p-channel and n-channel MOS field effect transistors in the logic gates on the odd stages are dropped whilst the gate voltages GP2, GN2, GP4, GN4, GP2k, and GN2k to be applied to the gates of the p-channel and n-channel MOS field effect transistors in the logic gates on the even stages are risen.
The above oscillator circuit has the following disadvantages. As compared to when the ring-oscillator simply comprises invertors, the current driving ability of the above oscillator circuit is lower by the ON-resistance of the MOS field effect transistors in the logic gates. Variable ranges of the oscillation frequency and the duty ratio of the above oscillator circuit are limited by the maximum current driving ability of each of logic gates which form the ring oscillator, for which reason it is required that the gate width of the MOS field effect transistors and the invertors in the logic gates are widen. This means that of the operational frequency is large, the gate width is large or widen whereby the occupied area of the oscillator circuit is large.
Subsequently, a conventional delay circuit will be described as follows. FIG. 2 is a circuit diagram illustrative of a conventional delay circuit. The conventional delay circuit has a series connection of invertors on j-stages (j: is even not less than 2) between input and output terminals.
The first stage invertor comprises a first series connection of three p-channel MOS field effect transistors TPa1, TPb1, and TPc1 and a second series connection of three n-channel MOS field effect transistors TNa1, TNb1 and TNc1. The gates of the p-channel and n-channel MOS field effect transistors TPa1, TPb1, TPc1, TNa1, TNb1 and TNc1 are connected to the input terminal. The first series connection of the three p-channel MOS field effect transistors TPa1, TPb1 and TPc1 are connected between the high voltage line and an output terminal of the first stage invertor. The second series connection of the three n-channel MOS field effect transistors TNa1, TNb1 and TNc1 are connected between the ground line and an output terminal of the first stage invertor.
The second stage invertor comprises a third series connection of three p-channel MOS field effect transistors TPa2, TPb2 and TPc2 and a fourth series connection of three n-channel MOS field effect transistors TNa2, TNb2 and TNc2. The gates of the p-channel and n-channel MOS field effect transistors TPa2, TPb2, TPc2, TNa2, TNb2 and TNc2 are connected to the input terminal of the second stage invertor. The third series connection of the three p-channel MOS field effect transistors TPa2, TPb2 and TPc2 are connected between the high voltage line and an output terminal of the second stage invertor. The fourth series connection of the three n-channel MOS field effect transistors TNa2, TNb2 and TNc2 are connected between the ground line and an output terminal of the second stage invertor.
The other stage invertor has the same circuit configuration as described above.
The current driving ability of each of the invertors is inversely proportional to the sum of the ON-resistances of the transistors connected in series. As compared to when each the inventors comprises a pair of p-channel and n-channel MOS field effect transistors, the current driving ability of the above delay circuit is low.
In addition, the capacitance to be driven by the each invertor on one stage is the gate capacitance of the invertor on the next stage to the one stage, for which reason the capacitance of the next stage is large due to the fact that the each invertor comprises series connections of the six MOS field effect transistors.
Further, since the transistors are connected in series, then the threshold voltages of the p-channel and n-channel MOS field effect transistors TNan and TPan (1.ltoreq.n.ltoreq.j) connected to the output terminal of the each invertor are higher than the threshold voltages of the p-channel and n-channel MOS field effect transistors TNcn and TPcn (1.ltoreq.n.ltoreq.j) connected to the ground line and the high voltage line.
The above three matters cause a relatively large delay of the delay circuit.
Another conventional delay circuit will subsequently be described prior to the descriptions of disadvantages of the above descried delay circuit. FIG. 3 is a circuit diagram illustrative of the other conventional delay circuit.
The other conventional delay circuit has a series connection of invertors on j-stages (j: is even not less than 2) between input and output terminals.
The first stage invertor comprises a first series connection of a single p-channel MOS field effect transistor TPa1 and a second series connection of three n-channel MOS field effect transistors TNa1, TNb1 and TNc1. The gates of the p-channel and n-channel MOS field effect transistors TPa1, TNa1, TNb1 and TNc1 are connected to the input terminal. The first series connection of the single p-channel MOS field effect transistor TPa1 is connected between the high voltage line and an output terminal of the first stage invertor. The second series connection of the three n-channel MOS field effect transistors TNa1, TNb1 and TNc1 are connected between the ground line and an output terminal of the first stage invertor.
The second stage invertor comprises a third series connection of three p-channel MOS field effect transistor TPa2, TPb2 and TPc2 and a fourth series connection of three n-channel MOS field effect transistors TNa2. The gates of the p-channel and n-channel MOS field effect transistors TPa2, TPb2, TPc2 and TNa2 are connected to the input terminal of the second stage invertor. The third series connection of the three p-channel MOS field effect transistor TPa2, TPb2 and TPc2 are connected between the high voltage line and an output terminal of the second stage invertor. The fourth series connection of the single n-channel MOS field effect transistor TNa1 is connected between the ground line and an output terminal of the second stage invertor.
The odd stage invertor comprises a series connection of a single p-channel MOS field effect transistor between the high voltage line and the output terminal of this odd stage invertor as well as a series connection of three n-channel MOS field transistors between the ground line and the output terminal of this odd stage invertor.
In contrast, the even stage invertor comprises a series connection of three p-channel MOS field effect transistors between the high voltage line and the output terminal of this odd stage invertor as well as a series connection of a single n-channel MOS field effect transistor between the ground line and the output terminal of this even stage invertor.
Only the last stage inverter on the last stage, however, has a simple circuit configuration for avoiding a disturbance of the waveform of the output signals from the delay circuit. Namely, the last stage inverter comprises a pair of p-channel and n-channel MOS field effect transistors connected in series between the high voltage line and the ground line, wherein the p-channel MOS field effect transistor is connected between the high voltage line and the output terminal of the delay circuit whilst the n-channel MOS field effect transistor is connected between the ground line and the output terminal of the delay circuit.
In the above second conventional delay circuit, the invertors on the odd stages shown the fast rising speed and slow falling speed, whilst the invertors on the even stages show the slow rising speed and fast falling speed. Therefore, if the rising signal is inputted to the input terminal of the above delay circuit, then the rising signal will appear at the output terminal with a large delay. If, however, the fall signal is inputted to the input terminal, then the fall signal will appear at the output terminal without substantive delay.
The above two delay circuits also have the following disadvantages. Since the each invertor comprises series connections of many transistors, a large area of the delay circuit is required.
Further, once the delay time has been set in circuit design work, the delay times are likely to be varied due to variations on the manufacturing, variations in power voltage on operation and temperature variations. There has been no compensation way for compensating the variation in delay time of the delay circuit.
In the above circumstances, it had been required to develop a novel oscillator circuit and a delay circuit, both of which are free from the above disadvantages.